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0/12 ATLASES
UNIFIED LEARNING SYSTEM · 2026

Write the kernel.
Understand the system.
Prove it.

Twelve interactive atlases connect visual GPU foundations, tile-level programming, Blackwell-aware optimization, and distributed inference in a 12-week evidence route that makes supported architecture and backend boundaries visible.

View the 12 weeks
12unified atlases
12intensive weeks
5LLM operators
3evidence gates
LEARNING GRAPHONLINE
CUDATRITONMEMORYOPSGPU
KERNELNSIGHTCUTLASSINFERENCENCCL
ARCH Ada → Hopper → Blackwell → RubinTRACK 14–16 h/wMODE evidence-first
COMPANION APP · 3D EXPLORATION

GEX GPU Execution Explorer

Learn theory, code, and measurement methods in GPU Kernel Atlas; explore GPU components and execution steps through interactive 3D scenes and a timeline in GEX. Then apply what you learned in the labs here.

GEX uses conceptual educational models; it does not present a physical chip floorplan, cycle-accurate simulation, or measured performance results.

ASERDARGUN.COM · CONNECTED LEARNING

From kernel to system.

GPU provides the compute foundation of the learning system. Follow these paths by topic; each application runs independently and your progress is not transferred.

ARCHITECTURE APPLICABILITY

From baseline to preview.
Make support visible.

Each architecture label describes concept applicability and maturity; it does not assume that you own the newest hardware.

CoreSM89 / core baseline

Ada

Established core baseline for warp, memory, occupancy, and classic Tensor Core work.

CurrentSM90 / current

Hopper

Current foundation for TMA, warp-group MMA, distributed shared memory, and persistent scheduling.

CurrentSM100 · SM120 / current

Blackwell

SM100 and SM120 are distinct targets. Do not assume SM100 TMEM or cluster-aware paths apply to SM120; verify Tensor Core and FP4/FP8 support for the selected kernel.

PreviewSM107 / preview

Rubin

Preview material limited to capabilities documented by current first-party toolchains.

Preview content depends on supported toolchains.
Maturity

Separate maturity.
Bound the evidence.

First-party sources are refreshed before publication; document freshness, feature maturity, and architecture/backend applicability are evaluated separately.

Core

Core

Core: hardware-generation-independent skills and evidence required for completion.

Current

Current

Current: supported by fresh first-party evidence; architecture and backend applicability are verified separately.

Preview

Preview

Preview: an exploration path dependent on toolchain or hardware maturity; it is not a graduation requirement.

Interactive laboratories are educational simulations; they do not claim measured hardware results.

01
CORRECTNESS

A kernel is not complete without a reference, a shape/dtype matrix, and clean sanitizer results.

02
MEASUREMENT

No performance claim without warm-up, quantiles, profiler evidence, and a controlled baseline.

03
INTEGRATION

The real goal is a portfolio-grade operator that works in PyTorch, compile, and serving workloads.

ATLAS MAP

One application.
Twelve domains.

A route from visual foundations to capstone. Every atlas includes an interactive lab, a Concept Studio, a decision model, and an acceptance artifact.

12-WEEK INTENSIVE ROUTE

Learn step by step.
Progress with evidence.

Suggested pace: 14–16 hours per week. Explore concepts in the browser; produce working kernels, correctness tests, and measurement reports in your own GPU environment.

01
Capability & environment evidence

Record GPU/backend, compute capability, toolchain, and measurement context.

Foundation
02
SIMT → tile programming

Grid, warp collaboration, divergence, and tile-level problem decomposition.

CUDA
03
TMA & data movement

Coalescing, tensor descriptors, TMA/DSMEM applicability, and the TMEM boundary.

Memory
04
Structured Triton operators

torch.library, triton_op/wrap_triton, opcheck, and structured autotune.

Integration
05
Grouped GEMM & MoE

Grouped work assignment, routing, and profiler-backed operator selection.

Operators
06
Low-precision operators

FP8/MXFP8 scale metadata, accumulation, and quality guardrails.

Operators
07
Attention & block-scaled boundaries

Stable softmax, paged KV-cache, and FP4/FP8 applicability boundaries.

Operators
08
Expanded correctness gate

Reference, tolerance, alias/determinism, memcheck, racecheck, and TMEM guardrails.

Evidence
09
2026 Nsight evidence

Report merge, clustering, instruction mix, scoreboards, and CUDA Graph nodes.

Measurement
10
CUTLASS 4 & Blackwell awareness

C++/CuTe → PTX/SASS evidence, Tensor Cores, and architecture-gated persistent/grouped scheduling.

Optimization
11
Disaggregated inference & NCCL

Encode/prefill/decode, graph boundaries, DP/TP/PP/EP, and topology evidence.

Systems
12
Capstone & portfolio

TTFT/ITL/throughput report, two 15%+ fusions, and defense

Graduation
GRADUATION GATE
2×

CUDA/Triton dual implementation

≥15%

median gain across two fused kernels

3

Nsight studies

1

vLLM TTFT/ITL/ throughput report

≥80%

interview defense

These thresholds are suggested capstone targets, not guaranteed speedups or results measured by this application. Compare against a baseline on the same hardware and workload; report the result and bottleneck when the target is not reached.